EECS 470 – Verilog Processor

My major design experience class was EECS 470 – Computer Architecture. The final project is building a synthesize-able out-of-order processor in verilog.

My group designed a 2-way superscaler pipeline with prefetching, an advanced load-store queue with store-to-load forwarding, out-of-order loads, and mulitple outstanding load misses, a write-back cache, a branch target buffer and a return address stack. The final report can be found here.

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